Non-volatile memory (NVM) bitcells, such as eFUSE bitcells, have a single bitline for reading and writing operations to the bitcell and a single access transistor for read and write operations. However, read and write operations have different operational characteristics, which results in conflicts when designing the NVM bitcell. A conventional NVM bitcell will be described with reference to FIG. 1 below.
FIG. 1 is a circuit schematic illustrating a conventional non-volatile memory bitcell. An NVM bitcell 100 includes a fuse element 102 and an access transistor 104. The fuse element 102 is coupled to a bitline 112 and the access transistor 104. A gate of the access transistor 104 is coupled to a wordline 114.
Write operations in NVM bitcells involve large currents best handled by low resistance bitlines. Additionally, the access transistor for a write operation occupies a large die area to handle the large currents. Low resistance, large bitlines have a large capacitance. For example, some conventional bitlines have capacitances of several picoFarads.
Read operations in NVM bitcells involve small sensing currents best handled by low capacitance bitlines. Thus, a design conflict arises when designing an NVM bitcell for read and write operations. The large capacitance of the bitlines for write operations results in low read speeds and high average and surge read currents. As a result of the NVM bitcell sharing a single bitline for read and write operations, the NVM bitcell is unable to be designed for both high and low voltage operation. Additionally, operating multiple voltages (write voltage and read voltage) on a single bitline of the NVM bitcell increases complexity of peripheral circuitry coupled to the NVM bitcell.
Alternative designs for NVM bitcells include a differential arrangement. FIG. 2 is a circuit schematic illustrating a conventional non-volatile memory bitcell with differential sensing. An NVM bitcell 200 includes a fuse element 202 coupled to an odd bitline 206 and a fuse element 222 coupled to an even bitline 226. An access transistor 204 is coupled to the fuse element 202 and is controlled by an odd wordline 214. An access transistor 224 is coupled to the fuse element 222 and is controlled by an even wordline 234. Although the differential design can increase read performance, adding a second bitline increases the resistance of the bitlines because conducting line layers (e.g., metal layers) available on the die are shared by the odd bitline 206 and the even bitline 226. When fewer conducting line layers are assigned to a bitline, the resistance of the bitline increases.
Thus, there is a need for a more reliable and higher performance non-volatile memory bitcell.